Renesas DF71364AD80FPV

SH-280 МГц256 КБ (256К x 8)

Overview

CPU• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture• Instruction length: 16-bit fixed length for improved code efficiency• Load-store architecture (basic operations are executed between registers)• Sixteen 32-bit general registers• Five-stage pipeline• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles• C language-oriented 62 basic instructions

Bus state controller (BSC)• Address space: A maximum 1 Mbyte for each of two areas (CS0 and CS1) (Only in SH7132/SH7137)• 8-bit external bus (Only in SH7132/SH7137)• The following settable for each area independently   - Number of access wait cycles   - Idle wait cycle insertion   - Supports SRAM• Outputs a chip select signal according to the target area

Features

Applications

• Automatic control
• Equipment control
• Instrument control
• Toys
• Robots
• Radio
• Television
• Heater/Fan
• Calculator
• Kindle