NXP DSP56321VF200

Фиксированная точкаИнтерфейс хоста, SSI, SCI200 МГц576 кБ-40°C ~ 100°C (TJ)

Overview

The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56321VF200 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550 MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.

Internal Peripherals • Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs • Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) • Serial communications interface (SCI) with baud rate generator • Triple timer module • Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled

Features

Applications

• Financial signals
• Other sensor array processing
• Spectral density estimation
• Statistical signal processing
• Digital image processing, data compression
• Video coding, audio coding
• Image compression
• Signal processing for telecommunications
• Control systems
• Biomedical engineering