NXP 74AUP1G74DC,125

15.8ns @ 3.3V, 30pF0,8 В ~ 3,6 В

Overview

The 74AUP1G74DC is a positive-edge trigger D-type Flip-flop with set and reset. It comes with an individual data (D), clock, set (S\D) and reset (R\D) inputs and complementary Q and Q\ outputs. The S\D and R\D are asynchronous active low inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the low-to-high transition of the clock pulse. The D input must be stable one set-up time prior to the low-to-high clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 to 3.6V. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Features

74AUP Series
Bulk Package
Set(Preset) and Reset Function
Complementary Output Type
1 Number of Elements
1 Number of Bits per Element
315 MHz Clock Frequency
5.8ns @ 3.3V, 30pF Max Propagation Delay @ V, Max CL
Positive Edge Trigger Type
4mA, 4mA Current - Output High, Low
0.8V ~ 3.6V Voltage - Supply
Surface Mount Mounting Type
500 nA Current - Quiescent (Iq)
0.6 pF Input Capacitance