Microchip ZL30100QDG1

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Overview

The ZL30100QDG1 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100QDG1 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100QDG1 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.Simplified Block DiagramTypical ApplicationsSynchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXsClock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) busesLine Card synchronization for PDH system

Features

Applications

• Ethernet switch/router
• PCI Express 2.0/3.0
• Broadcast video/audio timing
• Processor and FPGA clocking
• Any-frequency clock conversion
• MSAN/DSLAM/PON
• Fibre Channel, SAN
• Telecom line cards
• 1 GbE and 10 GbE
• Servers, Storage, Search Acceleration